Bipolar transistor scaling for minimum switching delay and energy dissipation

Author

Stork, J.M.C.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

550

Lastpage

553

Abstract

A novel figure-of-merit to guide in the scaling of high-speed bipolar transistors is proposed. A method is described to relate the gate delay of a ring-oscillator to measurable device parameters analytically. The closed-form solution for an unloaded ECL (emitter coupled logic) gate agrees very well with published data of the past several years and with the results of circuit simulation. The formula for the basic current switch relates in a simple way the different device parameters and has been used to optimize device design for maximum speed and minimum energy dissipation.<>

Keywords

bipolar integrated circuits; bipolar transistors; emitter-coupled logic; integrated logic circuits; network synthesis; oscillators; basic current switch; circuit simulation; closed-form solution; device design optimisation; device parameters; emitter coupled logic; figure-of-merit; gate delay; high-speed bipolar transistors; maximum speed; measurable device parameters; minimum energy dissipation; minimum switching delay; ring-oscillator; scaling; unloaded ECL gates; Bipolar transistors; Circuit simulation; Closed-form solution; Coupling circuits; Delay; Energy dissipation; Logic circuits; Logic devices; Logic gates; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32874

Filename

32874