A 0.25 μm CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range

This paper describes a wide frequency range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 μm CMOS/SIMOX technology. This generator supports internal clock frequency to external clock frequency ratios of 2,4,8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 400 MHz. At 400 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW