Gate-level dual-threshold total power optimization methodology (GDTPOM) principle for designing high-speed low-power SOC applications

Author

Chen, R. ; Liu, R. ; Kuo, J.B.

Author_Institution

Dept of Elec. Eng, Nat. Taiwan Univ., Taipei, Taiwan

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

2164

Lastpage

2167

Abstract

This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology, has a 24.6% reduction in total power consumption.

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; logic design; low-power electronics; multiplying circuits; system-on-chip; GDTPOM; MTCMOS technology; gate-level dual-threshold total power optimization; high-speed low-power SOC design; multiplier circuit; size 90 nm; static timing analysis; CMOS technology; Circuit testing; Costs; Design optimization; Electronic design automation and methodology; Energy consumption; Flowcharts; Libraries; Optimization methods; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734997

Filename

4734997