Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor

Author

Nomura, Tadahiro ; Mori, Ryuhei ; Ito, Minora ; Takayanagi, Kota ; Ochiai, Toshihiko ; Fukuoka, Kazuki ; Otsuga, Kazuo ; Nii, Koji ; Morita, S. ; Hashimoto, Toshikazu ; Kida, T. ; Yamada, J. ; Tanaka, Hiroya

Author_Institution

Renesas Electron. Corp., Kodaira, Japan

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

We developed a Wide IO DRAM controller chip with Through Silicon Via (TSV) technology. Test circuitry is embedded in the micro-IOs placed between the fine pitch TSVs which can reject TSV connectivity failures prior to stacking process. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We achieved 12.8 GB/s operation, while IO power was reduced by 89 % compared to LPDDR3.

Keywords

DRAM chips; circuit optimisation; electric impedance; fine-pitch technology; integrated circuit noise; integrated circuit testing; three-dimensional integrated circuits; IO power; TSV connectivity failures; TSV technology; bit rate 12.8 Gbit/s; fine pitch TSV; frequency 1 GHz; microIOs; package-board impedance optimization; prebonding TSV tests; sampled fully digital noise monitor; stacking process; switching noise; test circuitry; testability improvement; through silicon via; wide IO DRAM controller chip; Capacitance; Impedance; Monitoring; Noise; Optimization; Random access memory; Through-silicon vias; TSV; Wide IO DRAM; fully digital noise monitor; impedance optimization; pre-bonding test; simultaneous switching noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658415

Filename

6658415