Analysis of CMOS compatible BIPMOS transistor

The merged bipolar and MOS concept is applied to a lateral DMOS transistor to analyse the BIPMOS behaviour by simulation techniques. It is analysed that specific on-resistance (Ron) of a lateral MOS transistor for fixed n-well doping increases by factor of 1.8 with changing drift-region length from 10 to 30 μm whereas the change in Ron is 2.6 times with N-well doping at constant drift region length. The merged structure and lateral DMOS transistor are also analysed to determine the relation of electrical parameters to physical parameters of the device. It is revealed that additional integration of LDMOST across the emitter-base of the bipolar section improves the turn-off of the BIPMOS transistor. BIPMOS structures with varying drift length and channel width are fabricated using CMOS processes and the n-well is formed by ion-implantation on a p-substrate. The channel region is formed by lateral diffusion of the n and p-well. Vertical doping is simulated for varying condition of process parameters. It is observed that rinsing of silicon wafer with iso-propyl alcohol prior to TCE oxidation yields low C-V shift and high dielectric breakdown resulting in uniform threshold voltage