DocumentCode
2154758
Title
n-well design for trench DRAM arrays
Author
Cottrell, P. ; Warley, S. ; Voldman, S. ; Leipold, W. ; Long, C.
Author_Institution
IBM Gen. Technol. Div., Essex Junction, VT, USA
fYear
1988
fDate
11-14 Dec. 1988
Firstpage
584
Lastpage
587
Abstract
The effects of n-well doping profile on the characteristics of SPT DRAM (substrate plate trench dynamic random access memory) data retention time are described and characterized. A retrograde n-well is shown to be desirable since it offers decreased well resistance without the modification of surface device characteristics. Retention time can be further improved with an n-well doping concentration that decreases monotically with increasing depth rather than a retrograde profile which has a doping peak below the silicon surface. An n-well with such a doping profile has superior median retention time and a reduced number of bits that fail a data retention test. This improvement has been demonstrated by the fabrication of 4-Mb SPT-cell DRAM arrays and test structures.<>
Keywords
VLSI; field effect integrated circuits; integrated circuit technology; integrated memory circuits; random-access storage; semiconductor doping; 4 Mbit; SPT DRAM; ULSI; VLSI; characteristics; data retention time; decreased well resistance; n-well doping concentration; n-well doping profile; retrograde n-well; substrate plate trench dynamic random access memory; test structures; trench DRAM arrays; CMOS technology; Capacitors; Doping profiles; Epitaxial growth; Implants; Isolation technology; Random access memory; Silicon; Substrates; Surface resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Type
conf
DOI
10.1109/IEDM.1988.32882
Filename
32882
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