Title :
3-dimensional stacked capacitor cell for 16 M and 64 M DRAMS
Author :
Ema, T. ; Kawanago, S. ; Nishi, T. ; Yoshida, S. ; Nishibe, H. ; Yabu, T. ; Kodama, Y. ; Nakano, T. ; Taguchi, M.
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
A second-generation three-dimensional stacked capacitor cell has been developed. This cell has two significant features. One is that the three-dimensional feature of the storage capacitor has been considerably enhanced by means of a fine structure. The other is that bit lines have been formed before storage capacitor formation. Either of these features will lead to the realization of 16 M DRAMs (dynamic random-access memories), and both will be necessary to realize 64 M DRAMs.<>
Keywords :
VLSI; field effect integrated circuits; integrated circuit technology; integrated memory circuits; random-access storage; 16 Mbit; 3D stacked capacitor cell; 64 Mbit; DRAMs; ULSI; dynamic random-access memories; features; fine structure; second-generation; three-dimensional stacked capacitor cell; Capacitance-voltage characteristics; Degradation; Electrodes; Fabrication; Impurities; Laboratories; MOS capacitors; MOSFETs; Parasitic capacitance; Random access memory;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32884
