Title :
A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure
Author :
Kimura, S. ; Kawamoto, Y. ; Kure, T. ; Hasegawa, N. ; Etoh, J. ; Aoki, M. ; Takeda, E. ; Sunami, H. ; Itoh, K.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
The authors introduce a diagonal active stacked capacitor cell with a highly packed storage node (DASH) for use in a 16-Mb DRAM (dynamic random access memory). This novel cell features a storage capacitor formed above a bit line and the diagonal active area, which provides a large storage capacitance, 35 fF/bit, in a cell size of 3.4 mu m/sup 2/. The average charge retention time measured using an experimental 2-kb array is 30 s at 40 degrees C, indicating that the DASH has a superior potential for application to 16-Mb DRAMs. The memory cell leakage current is controlled to the order of 10/sup -12/ A.<>
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 16 Mbit; 1E-12 A; 2 kbit; 30 s; 35 fF; 40 C; DASH; ULSI; bit-line structure; cell size; charge retention time; diagonal active stacked capacitor cell; dynamic random access memory; highly packed storage node; memory cell leakage current; stacked capacitor DRAM cell; storage capacitor; Capacitance; Capacitors; Charge measurement; Contacts; Current measurement; Electrodes; Fabrication; Laboratories; Random access memory; Time measurement;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32885
