Title :
A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOB
Author :
Duan, Yiping ; Alon, Elad
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA
Abstract :
This paper presents a 12.8GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6-bit ENOB in 65nm CMOS. The prototype utilizes multi-stage sampling and a cascode sampler circuit to enable greater than 25GHz 3dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm2 and consumes a total of 162mW from dual 1.2V/1.1V supplies.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS; ENOB; ERBW; cascode sampler circuit; effective resolution bandwidth; frequency 25 GHz; multistage sampling; time-interleaved SAR ADC; CMOS integrated circuits; Calibration; Capacitors; Clocks; Prototypes; Resistance; Switches;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658418
