The implementation methods of high speed FIR filter on FPGA

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.