Title :
A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs
Author :
Xiaochen Yang ; Payne, Roger ; Jin Liu
Author_Institution :
Univ. of Texas at Dallas, Richardson, TX, USA
Abstract :
A 10GS/s 6b time-interleaved ADC in 65nm CMOS is presented in this paper. A partially-active flash sub-ADC structure is proposed to improve the ADC power efficiency and a source-follower based boot-strap T&H circuit is proposed to reduce input kickback and improve the ADC bandwidth. The four-phase 2.5GHz clocks for the sub-ADCs are derived from a 5GHz Nyquist frequency input clock. This leads to accurate timing skew calibration based on duty-cycle calibration, improving the ADC effective resolution at high input frequencies. Measured SNDR is 34.3dB at low input frequencies and 32.0dB at the Nyquist input frequency. The ADC including the input clock buffer consumes 83mW with a FOM of 197fJ/conv-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; clocks; sample and hold circuits; ADC power efficiency; CMOS process; Nyquist frequency input clock; bootstrap T&H circuit; duty cycle calibration; four-phase clocks; frequency 2.5 GHz; frequency 5 GHz; input clock buffer; partially active flash sub-ADC structure; size 65 nm; source follower; storage capacity 6 bit; time-interleaved ADC; timing skew calibration; CMOS integrated circuits; Calibration; Clocks; Frequency measurement; Logic gates; Semiconductor device measurement; Timing;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658419
