Differential power analysis and differential fault attack resistant AES algorithm and its VLSI implementation

This paper proposes an AES algorithm against both differential power analysis and differential fault analysis and its hardware implementation. This new algorithm emphasizes the feature of defending hardware against two kinds of side-channel attack simultaneously. Since the modified AES algorithm is much more complex than the original one, this paper exploits low hardware cost architecture to realize it. Furthermore, a pipelined structure is adopted to achieve high throughput. Simulations show that this architecture can protect hardware against both differential power analysis and differential fault attack. Synthesis result demonstrates that this design achieves adequately high data throughput with low hardware cost.