Title :
TCAD simulation study of independent gate junctionless FET-based flash memory
Author :
Srinivasan, R. ; Ambika, R.
Author_Institution :
Dept. of IT, SSN Coll. of Eng., Kalavakkam, India
Abstract :
In this paper, typical floating gate flash memory is simulated and studied using independent gate junction-less FET. TCAD simulator is used for generating the memory structure as well as for studying its programming, erasing and reading behaviour. Programming and erasing delays are 1.6 ms and 1.53 ms respectively for 25 nm fin width device. Programming and erasing voltages are +9 V and -15 V respectively. It has been observed that higher fin width devices show lesser delay. Out of the two control gates one is used for programming, erasing and reading operations. The other control gate is used to modulate the programmed and erased threshold voltages during reading operation. The difference between the programmed and erased cell is independent of the bias applied at the other control gate.
Keywords :
circuit simulation; field effect transistors; flash memories; technology CAD (electronics); TCAD simulation study; TCAD simulator; control gates; erased cell; erased threshold voltages; erasing behaviour; erasing delays; erasing operations; erasing voltages; fin width devices; floating gate flash memory; independent gate junction-less FET; independent gate junctionless FET-based flash memory; memory structure; programmed cell; programmed threshold voltage; programming behaviour; programming delays; programming operations; programming voltages; reading behaviour; reading operations; size 25 nm; time 1.53 ms; time 1.6 ms; voltage -15 V; voltage 9 V; Logic gates; Nanoscale devices; Performance evaluation; Threshold voltage; CHARGE; FLASH MEMORY; JUNCTION-LESS FET; TCAD; THRESHOLD VOLTAGE;
Conference_Titel :
Computing, Electronics and Electrical Technologies (ICCEET), 2012 International Conference on
Conference_Location :
Kumaracoil
Print_ISBN :
978-1-4673-0211-1
DOI :
10.1109/ICCEET.2012.6203927
