Research and implementation of high-speed reconfigurable grain algorithm

A high-speed and dynamic reconfigurable hardware architecture of grain algorithm is presented, which can satisfy the different characteristic of Grain-80 and Grain-128 algorithm. To save the hardware cost and get shorter critical path, we proposed tree network to implement linear and nonlinear feedback function. As to the different high-speed method, this paper perform detailed comparison and analysis. The design has been realized using Altera¿s FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18 ¿m CMOS process, the result proves the critical throughput rate can achieve 3.41 Gbps.