Non-volatile register based on hybrid spintronics/CMOS technology

In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90 nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500 ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.