Non-volatile register based on hybrid spintronics/CMOS technology

Author

Zhao, Weisheng ; Belhaire, Eric ; Chappert, Claude ; Javerliac, Virgile ; Mazoyer, Pascale

Author_Institution

IEF, CNRS, Orsay, France

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

2136

Lastpage

2139

Abstract

In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90 nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500 ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.

Keywords

CMOS logic circuits; MRAM devices; SPICE; application specific integrated circuits; field programmable gate arrays; magnetic tunnelling; magnetoelectronics; ASIC; CMOS; FPGA; MRAM; MTJ; Spice; logic circuits; nonvolatile register; spintronics; CMOS technology; Delay; Logic circuits; Magnetic switching; Magnetic tunneling; Magnetoelectronics; Material storage; Nonvolatile memory; Registers; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4735018

Filename

4735018