A floorplanning algorithm for block placement in SoC design

With the dramatic increase in size and complexity of systems on chip (SoC), there might be as much as hundreds of macro blocks and millions of standard cells integrated into a single chip. To facilitate signal routing and P/G network construction, one approach is to place macros around the boundary of chip and the remainder is used for arrangement of standard cells. To deal with such kind of placement, we propose an algorithm based on simulated annealing using B*-tree. The proposed algorithm guarantees a feasible solution through perturbation of B*-tree and the experimental results prove it very efficient.