• DocumentCode
    2155196
  • Title

    SRAM read current variability and its dependence on transistor statistics

  • Author

    Venugopalan, Sarad ; Joshi, Vinayak ; Zamudio, Luis ; Goldbach, Matthias ; Burbach, Gert ; van Bentum, Ralf ; Balasubramanian, S.

  • Author_Institution
    Dept. of EECS, Univ. of California, Berkeley, Berkeley, CA, USA
  • fYear
    2013
  • fDate
    22-25 Sept. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Our study breaks down the dependence of SRAM read current (Iread) variability (σIread) into constituting pass-gate (PG) and pull down (PD) NMOS transistor variability. We report a bottoms-up model for σIread including feedback in stacked transistors and discuss its implications on SRAM performance.
  • Keywords
    MOSFET circuits; SRAM chips; SRAM performance; SRAM read current variability; bottoms-up model; pass-gate NMOS transistor variability; pull down NMOS transistor variability; stacked transistors; transistor statistics; Hardware; Logic gates; Mathematical model; Negative feedback; Random access memory; Transistors; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2013 IEEE
  • Conference_Location
    San Jose, CA
  • Type

    conf

  • DOI
    10.1109/CICC.2013.6658430
  • Filename
    6658430
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2155196