DocumentCode :
2155249
Title :
Implement “Mesh+Local Trees” clock design flow in encounter
Author :
Qin Gu ; Gu, Jhen-Fong ; Brianli
Author_Institution :
Cadence ICD, Shanghai, China
fYear :
2008
fDate :
20-23 Oct. 2008
Firstpage :
2288
Lastpage :
2291
Abstract :
In this paper, we develop a novel way to achieve Mesh+Local Trees (MLT) flow in encounter. By blending the advantages of CTS and ClockMesh into one clock design flow, MLT is guaranteed to have smaller skew, and further optimize mesh structure to achieve lower power. MLT provides real loading sum value instead of estimating for global Mesh structure; another feature of this flow is that it provides basic support for MSV clock design.
Keywords :
clocks; network synthesis; trees (mathematics); Encounter; clock design flow; local trees; mesh structure; real loading sum value; Application specific integrated circuits; Automation; Chip scale packaging; Clocks; Design optimization; Energy consumption; Power dissipation; Robustness; Routing; Signal synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
Type :
conf
DOI :
10.1109/ICSICT.2008.4735027
Filename :
4735027
Link To Document :
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