Complementary p- and n-channel quantum-well MI/sup 3/SFETs

Heterostructure design and device fabrication techniques in GaAs/AlGaAs for vertically integrated p- and n-channel quantum-well FETs are described, and the operation of FETs fabricated on a p/n double-quantum-well heterostructure is demonstrated. The dependence of parasitic resistance and gate leakage on heterostructure layer parameters and device geometry is examined in experiments. Contact and n/sup +/ sheet resistances as low as 0.2 Omega -mm and 385 Omega / Square Operator , respectively, and peak transconductance values of 300 mS/mm are achieved in the best 1.5- mu m n-FETs at 77 K. p-FETs fabricated on a double-quantum-well heterostructure by Zn diffusion show contact and p/sup +/ sheet resistances of approximately 0.5 Omega -mm and 200 Omega / Square Operator , respectively, with peak transconductance of 80 mS/mm for 1.5- mu m gates at 77 K. Gate leakage is sufficiently low in both p- and n-FETs to allow high-speed complementary logic and memory at supply voltages of 1.1 V.<>