Fully integrated LVD clock generation/distribution IC

Author

Emeigh, Roger ; Strom, Jim

Author_Institution

IBM Corp., Rochester, MN, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

53

Lastpage

56

Abstract

This paper describes a clock generation and distribution IC, The design contains a fully differential PLL with a 1 GHz VCO and programmable dividers to form a frequency synthesizer with two synchronous output frequencies from 7.7 MHz to 500 MHz. LVD, low voltage differential, output drivers provide 12 low skew copies of the synthesized frequency with on chip termination. The module can be used as either a frequency synthesizer and distributor or as a distributor alone. The design obtains +/-20 ps cycle-cycle jitter, 40 ps driver-driver skew and 180 ps chip to chip skew. The fully integrated design is implemented on a 2.85 mm by 3.3 mm chip in a 3.3 V, 0.45 um L _eff BiCMOS technology with 12 GHz f_t npn´s and is packaged in a 68 pin PLCC

Keywords

BiCMOS digital integrated circuits; clocks; digital phase locked loops; dividing circuits; frequency synthesizers; integrated circuit design; jitter; pulse generators; voltage-controlled oscillators; -20 to 20 ps; 0.45 micron; 1 GHz; 12 GHz; 180 ps; 3.3 V; 40 ps; 7.7 to 500 MHz; BiCMOS technology; LVD clock generation/distribution IC; VCO; chip to chip skew; cycle-cycle jitter; driver-driver skew; frequency synthesizer; fully differential PLL; low-voltage differential; on chip termination; programmable dividers; synchronous output frequencies; BiCMOS integrated circuits; Clocks; Frequency conversion; Frequency synthesizers; Integrated circuit synthesis; Jitter; Low voltage; Phase locked loops; Synchronous generators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606584

Filename

606584