A macromodel solver for power distribution network analysis

This paper presents a solver to build macromodel of cell-based logic block for hierarchical power distribution network analysis. It first reduces logic block circuit model with circuit combination and capacitor equivalent transformation, and then build macromodel by the method of equivalent circuit. At last, node voltages are calculated by back solving. By building logic block macromodel, computation node number could be reduced sharply in high level analysis, it helps to reduce computation complexity and runtime .Experiment results show that the speed improvement of the solver is 4 times faster than HSPICE with less than 5.35e-6 error and it¿s optimal to model logic cell as time varying current source for worst case analysis is pessimistic and impractical.