Title :
Advanced self-alignment process technique with very thick sidewall for high speed GaAs LSIs
Author :
Tsunotani, M. ; Yamamoto, N. ; Kimura, T. ; Inokuchi, K. ; Sano, Y.
Author_Institution :
Oki Electr. Ind. Co. Ltd., Tokyo, Japan
Abstract :
The authors describe the performance of 0.5- mu m-gate GaAs MESFETs with the two-step n/sup +/ structure, which consists of shallowly doped n/sup +/ and deeply doped n/sup ++/ regions. To realize such a structure, a very-thick-sidewall process was developed. The maximum transconductance was as high as 420 mS/mm, and the standard deviation of the threshold voltage was as low as 26.4 mV over a 3-in wafer. The minimum propagation delay time of a directly-coupled FET-logic inverter IC implemented with this technology was 11.0 ps/gate at a power dissipation of 25.2 mW/gate. A 1/8 static frequency divider operated at a frequency of up to 16 GHz, and a D-type flip-flop recorded at a data rate of 10 Gb/s.<>
Keywords :
III-V semiconductors; Schottky gate field effect transistors; counting circuits; field effect integrated circuits; flip-flops; gallium arsenide; integrated logic circuits; large scale integration; logic gates; 0.5 micron; 10 Gbit/s; 11 ps; 16 GHz; 26.2 mW; 3 in; 420 mS/mm; D-type flip-flop; GaAs; MESFETs; data rate; directly-coupled FET-logic inverter; frequency; high speed GaAs LSIs; performance; power dissipation; propagation delay time; self-alignment process technique; static frequency divider; thick sidewall process; threshold voltage; transconductance; two step structure drain DCFL; two step structure source; Etching; Frequency conversion; Gallium arsenide; Ion implantation; Large scale integration; MESFETs; Plasma applications; Substrates; Threshold voltage; Transconductance;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32909
