DocumentCode :
2155678
Title :
Design space exploration for 3D integrated circuits
Author :
Xie, Yuan ; Ma, Yuehun
Author_Institution :
Pennsylvania State Univ., University Park, PA, USA
fYear :
2008
fDate :
20-23 Oct. 2008
Firstpage :
2317
Lastpage :
2320
Abstract :
Three-dimensional integrated circuit (3D IC) is emerging as an attractive option for overcoming the barriers in interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology. 3D IC offers the advantages of high performance, low power, smaller form-factor, and heterogeneous integration benefits. However, to enable the wide adoption of the 3D integration technology, there exist many challenges that need to be addressed. First, cost analysis at the early design stage to help the decision making on whether 3D integration should be used for the application is very critical. EDA design tools are the key to enable effective 3D IC designs; design space exploration at the architecture design is also important to fully take advantages that 3D offers. This article provides a tutorial on the design tools and methodologies to help design space exploration in 3D IC designs.
Keywords :
CMOS integrated circuits; integrated circuit design; 3D IC designs; CMOS technology; EDA design tools; architecture design; three-dimensional integrated circuit; CMOS technology; Costs; Decision making; Design methodology; Electronic design automation and methodology; Integrated circuit interconnections; Integrated circuit technology; Space exploration; Space technology; Three-dimensional integrated circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
Type :
conf
DOI :
10.1109/ICSICT.2008.4735042
Filename :
4735042
Link To Document :
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