Title :
Cluster-based Placement for multilevel hierarchical FPGA
Author :
Dai, Hui ; Zhou, Qiang ; Bian, Linian ; Wang, Yanhua
Author_Institution :
Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing, China
Abstract :
In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.
Keywords :
field programmable gate arrays; logic design; pattern clustering; V-shape flow; benchmark designs; bottom-up clustering process; cluster-based placement algorithm; field programmable gate arrays; logic utilization; multilevel hierarchical FPGA; top-down placement process; total wire-length; Algorithm design and analysis; Application specific integrated circuits; Clustering algorithms; Computer architecture; Computer science; Field programmable gate arrays; Logic design; Predictive models; Routing; Switches;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4735045
