Title :
A high utilization rate routing algorithm for modern FPGA
Author :
Xie, Ding ; Lai, Jimmei ; Tong, Jiarong
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Abstract :
Different from older generation of FPGAs, routing resources of recent FPGAs are described by hierarchical general routing matrix (GRM). In this paper, we present a routing algorithm which utilizes routing resources more efficient for GRM based FPGAs. First, we build routing resource graph (RRG) by a bottom-up way, then we combine breadth-first search manner with A* directed by a certain proportion to enhance utilization rate of routing resources, and this routing algorithm has high-adaptability to latest FPGA routing architectures. The experiment result shows that the utilization rate of hex lines and long lines has been raised by 6% and 9% respectively.
Keywords :
field programmable gate arrays; matrix algebra; network routing; breadth-first search manner; general routing matrix; high utilization rate routing; modern FPGA; routing resource graph; routing resources; Application specific integrated circuits; Delay; Field programmable gate arrays; Laboratories; Logic functions; Programmable logic arrays; Routing; Switches; Tiles; Wire;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4735047
