DocumentCode
2155918
Title
Submicron BiCMOS well design for optimum circuit performance
Author
Chapman, R.A. ; Bell, D.A. ; Eklund, R.H. ; Havemann, R.H. ; Harward, M.G. ; Haken, R.A.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1988
fDate
11-14 Dec. 1988
Firstpage
756
Lastpage
759
Abstract
The optimization of a submicron BiCMOS well design is described. The use of buried layers, a thin intrinsic epi layer, and a double n-well implant creates steeply graded well profiles which result in improved circuit performance due to lower diode capacitance. High contact resistance to the buried n+ layer is avoided by using a novel polysilicon plug contact process which also eliminates lateral n+ diffusion, enabling the base-to-collector design rule to be shrunk by more than 25%.<>
Keywords
BIMOS integrated circuits; integrated circuit technology; BiCMOS well design; IC process; buried layers; buried n+ layer; diode capacitance reduction; double n-well implant; optimum circuit performance; polycrystalline Si; polysilicon plug contact process; steeply graded well profiles; submicron BiCMOS; thin intrinsic epi layer; Annealing; BiCMOS integrated circuits; Breakdown voltage; Capacitance measurement; Circuit optimization; Diodes; Implants; Instruments; Plugs; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Type
conf
DOI
10.1109/IEDM.1988.32922
Filename
32922
Link To Document