High performance LSI process technology: SST CBi-CMOS

Author

Kobayashi, Yoshiji ; Yamaguchi, Chikara ; Amemiya, Yoshihito ; Sakai, Tetsushi

Author_Institution

LSI Lab., NTT, Atsugi-shi, Japan

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

760

Lastpage

763

Abstract

A CBi-CMOS IC, with complementary high-performance bipolar and CMOS on the same wafer, is reported. The structure is based on a self-aligned high-speed bipolar process called super self-aligned process technology or SST. The fabrication process is described, and its feasibility is confirmed by evaluating some devices fabricated by this technology. With a single 5-V supply, a propagation time delay of 160 ps has been measured for a 1- mu m-gate-length CMOS ring oscillator. n-p-n and p-n-p transistors have also been fabricated with f/sub T/ values of 16.9 and 7.5 GHz, respectively.<>

Keywords

BIMOS integrated circuits; integrated circuit technology; large scale integration; 1 micron; 16.9 GHz; 160 ps; 5 V; 7.5 GHz; LSI process technology; SST; complementary bipolar process; fabrication process; n-p-n transistors; p-n-p transistors; propagation time delay; ring oscillator; single 5-V supply; super self-aligned process technology; CMOS technology; Electrodes; Ion implantation; Laboratories; Large scale integration; MOS devices; Parasitic capacitance; Ring oscillators; Substrates; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32923

Filename

32923