A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization

A dithering technique for linearization of VCO-based ADCs is proposed. The proposed technique conditions the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO non-linearity. The technique, thus obviates the need for power-hungry digital calibration techniques or expensive front-end loop-filters. A prototype implementation (in 65nm CMOS) based on the technique achieves 10-b ENOB in digitizing signals with 50MHz bandwidth consuming 8.2mW at an FoM of 90fJ/conv.step.