An alternative gate electrode material of fully depleted SOI CMOS for low power applications

Author

Hsiao, T.C. ; Wang, Albert W. ; Saraswat, Krishna ; Woo, Jason C S

Author_Institution

Dept. of Electr. Eng., California State Univ., Los Angeles, CA, USA

fYear

1997

fDate

6-9 Oct 1997

Firstpage

20

Lastpage

21

Abstract

Summary form only given. In this work, a variable gate work-function scheme was proposed, using a p⁺ polycrystalline SiGe/Si stack gate. The Ge composition is varied to achieve the desired threshold voltage while giving latitude in channel doping. Using this work-function engineering, a threshold voltage of 0.2 to 0.6 V can be easily obtained for sub-0.25 μm devices fabricated on ultra-thin film SOI. This technology can achieve near-symmetric threshold voltages for NMOS and PMOS devices with near-symmetric moderate channel doping concentration. This scalable gate work-function engineering can be an integral part of deep submicron SOI CMOS design and promises to achieve superior performance for low power electronics

Keywords

CMOS integrated circuits; MOSFET; integrated circuit technology; silicon-on-insulator; work function; 0.2 to 0.6 V; 0.25 micron; Ge composition variation; NMOS devices; PMOS devices; SiGe-Si; channel doping concentration; deep submicron SOI CMOS design; fully depleted SOI CMOS; gate electrode material; low power applications; p⁺ polycrystalline SiGe/Si stack gate; scalable gate work-function engineering; threshold voltage; ultra-thin film SOI; variable gate work-function scheme; CMOS technology; Design engineering; Doping; Electrodes; Germanium silicon alloys; Low power electronics; MOS devices; Power engineering and energy; Silicon germanium; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1997. Proceedings., 1997 IEEE International

Conference_Location

Fish Camp, CA

ISSN

1078-621X

Print_ISBN

0-7803-3938-X

Type

conf

DOI

10.1109/SOI.1997.634912

Filename

634912