Title :
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator
Author :
Wonsik Yu ; KwangSeok Kim ; SeongHwan Cho
Author_Institution :
Dept. of EE, KAIST, Daejeon, South Korea
Abstract :
This paper presents an all-digital second-order ΔΣ time-to-digital converter (TDC) by using switched-ring oscillator (SRO) and gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using the SRO, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the SROs. The prototype TDC achieves 148fsrms integrated noise and 80.4dB dynamic range in 4MHz signal bandwidth at 400MS/s while consuming 6.55mW in a 65nm CMOS process.
Keywords :
CMOS digital integrated circuits; delta-sigma modulation; error compensation; oscillators; time-digital conversion; CMOS process; GSRO; MASH TDC; bandwidth 4 MHz; error compensation; gated switched-ring oscillator; integrated noise all-digital second-order ΔΣ time-to-digital converter; multistage noise-shaping TDC; power 6.55 mW; size 65 nm; time 148 fs; Bandwidth; Logic gates; Multi-stage noise shaping; Noise; Oscillators; Radiation detectors;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658464
