Design metrics for blind ADC-based wireline receivers

ADC-based receivers use an ADC in the front end to convert the incoming signal to digital where significant equalization can be done in digital domain. These receivers can be classified as phase-tracking and blind architectures. In the former, the VCO phase is controlled through a feedback loop so as to sample the received data in the middle of the data eye. In the latter, the received signal is sampled with a blind clock, i.e. not in a loop, and the data at the center is obtained by data processing techniques such as data interpolation and extrapolation. This paper compares the two architectures in terms of their design complexity and cost, and derives equations that relate the required ADC resolution to channel loss and to the characteristics of the FFE/DFE that follow the ADC.