Power optimization in ΣΔ ADC design

Author

Bajdechi, Ovidiu ; Huijsing, Johan H. ; Gielen, Georges

Author_Institution

Delft Univ. of Technol., Netherlands

Volume

1

fYear

2002

fDate

2002

Firstpage

353

Abstract

A power optimization method for sigma-delta (ΣΔ) analog-to-digital converters (ADCs) is presented. System-level considerations are taken into account to maximize the peak signal-to-(noise+distortion) ratio (SNDR) versus power consumption. Both continuous-time (CT) and discrete-time (DT) loop filters are analyzed. The power consumption of CT and DT integrators is calculated and the best combination of CT/DT integrators is used. This concept is applied in designing a mixed CT/DT ΣΔ ADC for telephony applications. The ADC has a power consumption of only 1.7 mW while operating with a single supply voltage of 1.8 V. A bandgap reference is integrated on-chip to reduce the number of external connections.

Keywords

continuous time filters; discrete time filters; integrated circuit design; integrating circuits; power consumption; sigma-delta modulation; telephone equipment; ΣΔ ADC; 1.7 mW; 1.8 V; 11 kHz; SNR; bandgap reference; continuous-time loop filters; discrete-time loop filters; integrators; power consumption; power optimization; sigma-delta ADC; sigma-delta analog-to-digital converters; signal-to-noise ratio; signal-to-noise+distortion ratio; telephony; Analog-digital conversion; Analytical models; Circuit simulation; Design optimization; Energy consumption; Filters; Frequency conversion; Photonic band gap; Telephony; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Signal Processing, 2002. DSP 2002. 2002 14th International Conference on

Print_ISBN

0-7803-7503-3

Type

conf

DOI

10.1109/ICDSP.2002.1027902

Filename

1027902