Salicide process for 400 Å fully-depleted SOI-MOSFETs using NiSi

Summary form only given. The salicide process is a well-known technique to reduce source/drain and gate resistances of SOI-MOSFETs. However, it is becoming increasingly difficult to implement as the Si layer thickness is scaled to less than 500 Å. The amount of Si that can be consumed during the salicide process should be less than the thickness of the Si layer. Once the Si consumption exceeds the amount of the Si layer, voids occur at the silicide/silicon interface beneath the oxide spacers and the silicide encroaches laterally beneath the spacer. It is important to form a thermally stable thin silicide only a few hundred Å thick. In this paper, we demonstrate that Ni is a very suitable candidate for a salicide process on very thin (400 Å) fully-depleted SOI-MOSFETs. Source/drain resistances of NMOS and PMOS transistors on SIMOX substrates with values of 500 Ω-μm and 800 Ω-μm have been achieved, which are among the best values ever reported. We also have theoretically evaluated the thermal effects of the salicide process