DocumentCode
2156651
Title
High performance dual-gate FD-SOI CMOS process with an ultra thin TiSi2
Author
Nakamura, H. ; Imai, K. ; Onishi, H. ; Kumagai, K. ; Yamada, T. ; Iwaki, K. ; Matsubara, Y. ; Ishigami, T. ; Furosawa, S. ; Horiuchi, T.
Author_Institution
ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan
fYear
1997
fDate
6-9 Oct 1997
Firstpage
24
Lastpage
25
Abstract
Summary form only given. We have developed a manufacturable FD-SOI 0.35 μm CMOS process with an ultra thin TiSi2 film. We obtained sheet resistance of 10 Ω/sq. for N+ and P+ SOI diffusions, and saturation current of 1.8 mA and 0.56 mA for NMOS and PMOS transistors (VD=VG=1.5 V, W=10 μm), respectively. The feasibility of the process has been verified successfully by fabricating a 128 kbit SRAM
Keywords
CMOS integrated circuits; MOSFET; SRAM chips; integrated circuit manufacture; integrated circuit metallisation; silicon-on-insulator; titanium compounds; 0.35 micron; 0.56 mA; 1.5 V; 1.8 mA; 10 micron; 128 kbit; NMOS transistors; PMOS transistors; SRAM fabrication; Si; TiSi2; dual-gate FD-SOI CMOS process; fully-depleted CMOS process; high performance CMOS process; manufacturable submicron process; saturation current; sheet resistance; ultra thin TiSi2 film; Annealing; Argon; CMOS process; CMOS technology; MOS devices; MOSFET circuits; Random access memory; Silicon; Tin; Titanium;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1997. Proceedings., 1997 IEEE International
Conference_Location
Fish Camp, CA
ISSN
1078-621X
Print_ISBN
0-7803-3938-X
Type
conf
DOI
10.1109/SOI.1997.634914
Filename
634914
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