A novel low power static frequency divider based on the GDI technique

In this paper a low power divide-by-two static frequency divider using GDI D flip-flop is proposed which uses only single clock phase. So, the timing problem of complementary clock signals is relaxed. This divider is simulated in a standard 0.18 mum CMOS process. Simulation results indicate that the proposed divider consumes, in the worst case, 3.74 mW power at 3.3 V supply voltage and maximum operating frequency up to 7.3 GHz, and the power consumption is 10.7 muW by using of a 1 V supply voltage at 1 GHz input frequency.