A novel low power static frequency divider based on the GDI technique

Author

Saberkari, Alireza ; Shokouhi, Shahriar Baradaran ; Kiani, Azadeh ; Poorahangaryan, Fereshteh

Author_Institution

Dept. of Electr. Eng., Iran Univ. of Sci. & Technol., Tehran

fYear

2009

fDate

3-6 May 2009

Firstpage

67

Lastpage

70

Abstract

In this paper a low power divide-by-two static frequency divider using GDI D flip-flop is proposed which uses only single clock phase. So, the timing problem of complementary clock signals is relaxed. This divider is simulated in a standard 0.18 mum CMOS process. Simulation results indicate that the proposed divider consumes, in the worst case, 3.74 mW power at 3.3 V supply voltage and maximum operating frequency up to 7.3 GHz, and the power consumption is 10.7 muW by using of a 1 V supply voltage at 1 GHz input frequency.

Keywords

CMOS logic circuits; flip-flops; frequency dividers; low-power electronics; power dividers; CMOS process; D flip-flop; GDI technique; clock signal relaxation; frequency 1 GHz; low-power static frequency divider; power 10.7 muW; power 3.74 mW; size 0.18 mum; voltage 1 V; voltage 3.3 V; CMOS process; CMOS technology; Circuits; Clocks; Energy consumption; Flip-flops; Frequency conversion; Frequency measurement; MOSFETs; Power dissipation; D flip-flop; GDI; Static frequency divider; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2009. CCECE '09. Canadian Conference on

Conference_Location

St. John´s, NL

ISSN

0840-7789

Print_ISBN

978-1-4244-3509-8

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2009.5090094

Filename

5090094