Dynamic effects in BTG/SOI MOSFETs and circuits due to distributed body resistance

Summary form only given. The SOI MOSFET with body tied to gate (BTG) has been proposed for low-voltage CMOS applications. Clearly for DC or quasi-static conditions, the BTG device will have reduced threshold voltage (V_T) when on due to the body bias, and hence increased drive current. Thus BTG/SOI CMOS can conceivably be designed with nominal V_T high enough to avoid excessive static power while giving good speed performance. Thin-film SOI is the preferred technology for BTG MOSFETs because of minimal source/drain junction area and hence less recombination current in the gate. However, the effects of inherent body resistance in the BTG tie, which have not been addressed in depth, are an issue. In this paper, we present insightful results of circuit simulations that reveal dynamic effects of the finite and distributed body resistance and that give insight concerning optimal design of BTG/SOI CMOS devices and circuits