Advanced digital phase-locked loops

Analog PLLs do not scale down as process and are not amenable to noise-cancellation and other calibration algorithms; Digital PLLs exploit CMOS scaling and allow for simple, accurate implementation of digiphase and two-point modulation; Typically, DPLLs require TDCs with tight resolution to achieve low phase noise and fractional-spur level, which increase both power consumption and design effort; DPLLs with Bang-Bang Detectors (i.e. coarse midrise TDCs) in combination with a DTC allows same phase-noise performance and fractional-spur level at much lower power consumption; Fine resolution is only required to DCO and DTC, which can be both improved leveraging oversampling techniques ; Bang-Bang DPLLs achieve superior noise/ power trade-off over conventional DPLLs, while reducing design effort.