DocumentCode :
2157282
Title :
Design for nanoscale patterning
Author :
Gupta, Puneet
Author_Institution :
UCLA, Los Angeles, CA, USA
fYear :
2013
fDate :
22-25 Sept. 2013
Firstpage :
1
Lastpage :
52
Abstract :
Design and Lithography are co-developed Regularity (in all ways you can think of) is (almost) always helpful for patterning but can hurt density scaling Be prepared for increasingly unusual layout restrictions and electrical effects coming from lithography.
Keywords :
lithography; codeveloped regularity; density scaling; electrical effects; layout restrictions; lithography; nanoscale patterning design; Art; Companies; Layout; Manuals; Nanoscale devices; Performance evaluation; Systematics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
Type :
conf
DOI :
10.1109/CICC.2013.6658506
Filename :
6658506
Link To Document :
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