Title :
A K=3, 2 Mbps low power turbo decoder for 3rd generation W-CDMA systems
Author :
Suzuki, Hiroshi ; Wang, Zhongfeng ; Parhi, Keshab K.
Author_Institution :
LSI Div., Kawasaki Steel Corp., Chiba, Japan
Abstract :
This paper presents the design of a K=3, 2 Mbps turbo decoder chip targeted for 3rd generation wideband CDMA (W-CDMA) systems. This paper makes two contributions. First, finite precision effects on the decoder performance are analyzed and optimal word-lengths are determined. Second, novel power-down techniques are proposed, with which very high power-down efficiency can be achieved without significant performance degradation. The decoder has been designed and fabricated using a 0.25 μm standard cell library. The core size is 2.32 mm×1.72 mm and contains 300 K transistors
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; code division multiple access; decoding; digital signal processing chips; high-speed integrated circuits; low-power electronics; mobile radio; turbo codes; 0.25 micron; 2 Mbit/s; 32 MHz; W-CDMA systems; decoder chip; finite precision effects; low power turbo decoder; optimal word-lengths; power-down techniques; standard cell library; wideband CDMA systems; AWGN; Additive white noise; Application specific integrated circuits; Binary phase shift keying; Gaussian noise; Integrated circuit noise; Iterative decoding; Multiaccess communication; Power generation; Random variables;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852614
