DocumentCode
2157746
Title
Ultra low-power CMOS IC using partially-depleted SOI technology
Author
Ebina, Akihiko ; Kadowaki, Tadao ; Sato, Yoko ; Yamaguchi, Masayuki
Author_Institution
Semicond. Oper. Div., Seiko Epson Corp., Nagano, Japan
fYear
2000
fDate
2000
Firstpage
57
Lastpage
60
Abstract
We have developed an ultra low power IC for wrist-watch application. The realized operation current and voltage were 30 nA and 0.42 V respectively. This extremely low power operation was achieved by taking full advantage of body-floated devices with the partially-depleted SOI CMOS technology
Keywords
CMOS integrated circuits; clocks; integrated circuit design; low-power electronics; mixed analogue-digital integrated circuits; silicon-on-insulator; voltage regulators; 0.42 to 0.5 V; 30 nA; SOI CMOS technology; Si; body-floated devices; extreme low power operation; partially-depleted SOI technology; ultra low-power CMOS IC; wrist-watch application; Application specific integrated circuits; Batteries; CMOS integrated circuits; CMOS technology; Capacitance; Energy consumption; Power generation; Solar power generation; Threshold voltage; Watches;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5809-0
Type
conf
DOI
10.1109/CICC.2000.852617
Filename
852617
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