A new design for complete on-chip ESD protection

Author

Wang, Albert Z.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA

fYear

2000

fDate

2000

Firstpage

87

Lastpage

90

Abstract

The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V_DD, positive/negative from I/O to ground, and from V_DD to ground. This ultra-fast (t₁~0.16 nS) structure operates symmetrically. Measurements showed low holding voltage (~2 V), low discharging impedance (~Ω), and adjustable triggering voltages. ESD tests passed 14 kV (HBM). Design prediction was achieved by comprehensive ESD simulation. It is particularly good for RF ICs

Keywords

CMOS integrated circuits; UHF integrated circuits; electrostatic discharge; integrated circuit design; protection; 14 kV; ESD simulation; RF IC application; adjustable triggering voltages; electrostatic discharge protection structure; low discharging impedance; low holding voltage; on-chip ESD protection; symmetrical operation; ultra-fast structure; Contacts; Electrostatic discharge; Impedance; Partial discharges; Power engineering computing; Radio frequency; Radiofrequency integrated circuits; Resistors; Surge protection; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852624

Filename

852624