Quantitative characterization of substrate noise for physical design guides in digital circuits

Author

Nagata, Makoto ; Nagai, Jin ; Morie, Takashi ; Iwata, Atsushi

Author_Institution

Fac. of Eng., Hiroshima Univ., Japan

fYear

2000

fDate

2000

Firstpage

95

Lastpage

98

Abstract

Substrate noise is quantitatively evaluated by gain calibrated substrate voltage measurements in a 100 ps-100 μV resolution. Activity in a digital block is a key parameter to which the noise intensity is proportional, and its reduction is a straight and universal solution to suppress the noise. Use of Kelvin grounding in the source circuits and placing a guardband proximate to the receiver circuits together also attenuates the noise significantly, however, the effect is limited to the low frequency components such as ringing

Keywords

CMOS integrated circuits; VLSI; integrated circuit design; integrated circuit measurement; integrated circuit noise; mixed analogue-digital integrated circuits; ASIC design; Kelvin grounding; digital circuits; gain calibrated substrate voltage measurements; guardband placement; low frequency components; mixed signal circuits; noise intensity; noise suppression; physical design guide; quantitative characterization; receiver circuits; ringing; source circuits; substrate noise; Circuit noise; Crosstalk; Digital circuits; Grounding; Kelvin; Low-frequency noise; Noise figure; Noise generators; Noise reduction; Transmission line matrix methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852626

Filename

852626