Title :
Physical design of the MUSE wafer-scale circuit
Author :
Anderson, Allan H. ; Woodward, Charles E.
Author_Institution :
MIT Lincoln Lab., Lexington, MA, USA
Abstract :
MUSE is a wafer-scale adaptive nulling processor which is being implemented using the restructurable VLSI techniques and design tools. The authors describe the physical design of the wafer with emphasis on interconnect redundancy and design for testability during the restructuring process. Power distribution and the wafer floorplan and packaging are also discussed
Keywords :
VLSI; digital signal processing chips; redundancy; systolic arrays; MUSE wafer-scale circuit; adaptive nulling processor; design for testability; interconnect redundancy; packaging; physical design; power distribution; restructurable VLSI techniques; wafer floorplan; Adaptive systems; Adders; Clocks; Design for testability; Digital signal processors; Integrated circuit interconnections; Laboratories; Radar antennas; Very large scale integration; Wiring;
Conference_Titel :
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9126-3
DOI :
10.1109/ICWSI.1991.151689
