DocumentCode
2158044
Title
Design for manufacturing layout analyses correlate layout to physico-chemical yield loss mechanisms
Author
Tan, Cheng Peng ; Congshu Zhou ; Yi Tian ; Chang Liu ; Hein-Mun Lam ; Jian Zhang ; Lu, Min
Author_Institution
GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore, Singapore
fYear
2013
fDate
22-25 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
We introduce a case-based learning workflow in the foundry for managing layout weakpoints and implementing layout analyses checks. In this work, we describe case studies that demonstrate how layout analyses can be used to detect layout weakpoints and correlate them to actual physico-chemical mechanisms behind defects observed on silicon.
Keywords
elemental semiconductors; integrated circuit design; integrated circuit yield; silicon; Si; case-based learning workflow; foundry; layout weakpoints detection; manufacturing layout analysis; physicochemical yield loss mechanisms; silicon; Dielectrics; Films; Foundries; Layout; Manufacturing; Metals;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location
San Jose, CA
Type
conf
DOI
10.1109/CICC.2013.6658535
Filename
6658535
Link To Document