Timing abstraction of intellectual property blocks

This paper describes a method for creating timing models of large blocks (>5,000 transistors) based on the use of static timing analysis. This method captures the block´s propagation delays and the slew rates at its outputs. More importantly, it abstracts all the internal setup, hold, and loop constraints of the block. The resulting block timing model can thus be used as an accurate representation of the block´s temporal behavior obviating the need for exposing the block´s internal implementation. Block characterization finds application in intellectual property encapsulation and in team design of large timing-constrained chips