Title :
Applying placement-based synthesis for on-time system-on-a-chip design
Author :
Lackey, David E.
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
This paper examines the fundamental issues in timing closure, using present-day methodologies, for designs enabled by System-on-a-Chip (SOC) silicon technologies. Placement-based synthesis is proposed as a method to address these issues, and its benefits are contrasted against the problems of current methods. Finally, this paper discusses application of placement-based synthesis for optimum benefit in enabling on-schedule SOC design
Keywords :
application specific integrated circuits; circuit layout CAD; elemental semiconductors; integrated circuit design; silicon; timing; Si; on-schedule SOC design; on-time system-on-a-chip design; placement-based synthesis; timing closure; Circuit synthesis; Delay estimation; Design methodology; Design optimization; Integrated circuit interconnections; Logic design; Microelectronics; Silicon; System-on-a-chip; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852631
