Title :
Methodology for I/O cell placement and checking in ASIC designs using area-array power grid
Author :
Buffet, Patrick H. ; Natonio, Joseph ; Proctor, Robert A. ; Sun, Yu.H. ; Yasar, Gulsun
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
Electrical rule checking is fundamental to achieve a good I/O cell placement. This paper presents the analysis techniques used to design a robust power-grid structure, the method used to make I/O cell placement guidelines, details of the I/O cell placement process and electrical checking algorithms
Keywords :
application specific integrated circuits; cellular arrays; circuit layout CAD; integrated circuit layout; logic arrays; ASIC designs; I/O cell placement; analysis techniques; area-array power grid; electrical checking algorithms; electrical rule checking; robust power-grid structure; Algorithm design and analysis; Application specific integrated circuits; CMOS technology; Copper; Electromigration; Inductance; Packaging; Power grids; Robustness; Sun;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852632
