DocumentCode
2158205
Title
Architecture of cluster-based FPGAs with memory
Author
Clifford, Jason P. ; Wilton, Steven J E
Author_Institution
Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
fYear
2000
fDate
2000
Firstpage
131
Lastpage
134
Abstract
Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster
Keywords
cellular arrays; embedded systems; field programmable gate arrays; cluster-based FPGAs; embedded memory; logic cluster; memory array; overall speed; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Memory architecture; Random access memory; Read-write memory; Registers; Switches; Switching circuits; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5809-0
Type
conf
DOI
10.1109/CICC.2000.852633
Filename
852633
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