Title :
Cypress Delta39KTM. A memory-rich, high performance, scalable CPLD architecture
Author :
Kennings, Andrew ; Mohammed, Haneef ; Skudlarek, Joseph P. ; Tian, Bing
Author_Institution :
Cypress Semicond., Beaverton, OR, USA
Abstract :
The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the WarpTM 6.0 software
Keywords :
cellular arrays; circuit layout CAD; integrated circuit layout; logic CAD; network routing; programmable logic arrays; Cypress Delta39K; I/O cells; PLL functions; Warp 6.0 software; dedicated track MUX-based routing architecture; hierarchical organization; macrocells; on-chip specialty memory; scalable CPLD architecture; Clocks; Computer architecture; Hardware; Integrated circuit interconnections; Logic devices; Macrocell networks; Packaging; Routing; Scalability; Software performance;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852634
