Title :
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core
Author :
Moongon Jung ; Taigon Song ; Yang Wan ; Young-Joon Lee ; Mohapatra, Debabrata ; Hong Wang ; Taylor, Gareth ; Jariwala, Devang ; Pitchumani, Vijay ; Morrow, Philip ; Webb, C. ; Fischer, P. ; Sung Kyu Lim
Author_Institution :
Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.
Keywords :
integrated circuit design; integrated circuit layout; low-power electronics; microprocessor chips; network routing; three-dimensional integrated circuits; 3D floorplanning; 3D integrated circuit design; OpenSPARC T2 core; buffer cell count; commercial-grade CPU core; functional unit block folding; intra-block-level routing; metal layer usage control; power consumption reduction; Clocks; Metals; Power demand; Routing; Three-dimensional displays; Timing; Wires;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658541
